verilog-library

Naming conventions

1. s_: Less Clock version
2. v_: Verilog special syntax

Subtractor

Half Subtractor

half_subtractor(input A, B, output Bo, D);

Full Subtractor

full_subtractor(input A, B, Bi, output Bo, D);

Other implementations

module s_full_subtractor(input A, B, Bi, output D, Bo);
  assign D = A ^ B ^ Bi;
  assign Bo = (~A & B) | (~(A ^ B) & Bi);
endmodule

module v_full_subtractor(input A, B, Bi, output D, Bo);
  assign {Bo, D} = A - B - Bi;
endmodule

Flip Flop

RS Flip Flop

NOR

rs_flip_flop(input R, S, output Q, Qbar);

NAND

nand_rs_flip_flop(input Rbar, Sbar, output Q, Qbar);

Adder

Full Adder

full_adder(input A, B, Ci, output Co, S)

Other implementations

module s_full_adder(input A, B, Ci, output Co, S);
  assign S = A ^ B ^ Ci;
  assign Co = (A & B) | ((A ^ B) & Ci);
endmodule

Verilog special syntax

module v_full_adder(input A, B, Ci, output Co, S);
  assign {Co, S} = A + B + Ci;
endmodule

Half Adder

half_adder(input A, B, output C, S);